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Features
* * * * * * * * * * * * * * * * *
3000 Dhrystone 2.1 MIPS at 1.3 GHz Selectable Bus Clock (30 CPU Bus Dividers up to 28x) 13 Selectable Core-to-L3 Frequency Divisors Selectable MPx/60x Interface Voltage (1.8V, 2.5V) Selectable L3 Interface of 1.8V or 2.5V PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating Conditions Nap, Doze and Sleep Modes for Power Saving Superscalar (Four Instructions Fetched Per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 Hexabytes (252) 64-bit Data and 32-bit Address Bus Interface Integrated L1: 32 KB Instruction and 32 KB Data Cache Integrated L2: 512 KB 11 Independent Execution Units and Three Register Files Write-back and Write-through Operations fINT Max = 1 GHz (1.2 GHz to be Confirmed) fBUS Max = 133 MHz/166 MHz
PowerPC 7457 RISC Microprocessor PC7457/47 Preliminary Specification -site
Description
This document is primarily concerned with the PowerPCTM PC7457; however, unless otherwise noted, all information here also applies to the PC7447. The PC7457 and PC7447 are implementations of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the PC7457. The PC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The PC7457 consists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high-bandwidth interface. The PC7447 is identical to the PC7457 except it does not support the L3 cache interface. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes may be used as cache; the remaining 2M bytes must be private memory. Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455 application if the core power supply is 1.3V.
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Screening
* * * CBGA Upscreenings Based on Atmel Standards Full Military Temperature Range (Tj = -55C, +125C), Industrial Temperature Range (Tj = -40C, +110C) CBGA Package, HiTCE Package for the 7447 TBC
CBGA 483
G suffix CBGA 360 Ceramic Ball Grid Array
GH suffix HITCE 360 Ceramic Ball Grid Array (TBC)
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Figure 1. PC7457 Microprocessor Block Diagram
Block Diagram
Additional Features
- Time Base Counter/Decrementer - Clock Multiplier - JTAG/COP Interface - Thermal/Power Management - Performance Monitor Completion Unit Completion Queue (16-Entry)
Instruction Unit Branch Processing Unit BTIC (128-Entry) BHT (2048-Entry) CTR Fetcher
Instruction Queue (12-Word)
Instruction MMU SRs (Shadow) 128-Entry ITLB
128-Bit (4 Instructions)
Tags
IBAT Array LR Dispatch Unit Data MMU SRs (Original) VR Issue (4-Entry/2-Issue) GPR Issue (6-Entry/3-Issue) FPR Issue (2-Entry/1-Issue) 128-Entry DTLB
32-Kbyte I Cache
96-Bit (3 Instructions)
Tags D Cache
32-Kbyte
DBAT Array
Reservation Stations (2-Entry) Completes up to three instructions per clock VR File 16 Rename Buffers Reservation Reservation Reservation Reservation v Station Station Station Station Reservation v Stations (2) Reservation Reservation Reservation Station Station Station Vector Touch Queue GPR File 16 Rename Buffers
EA
Load/Store Unit Vector Touch Engine + (EA Calculation) Finished Stores L1 Castout PA FPR File 16 Rename Buffers Reservation Stations (2)
Integer Unit 2 x/
Integer Integer Integer Unit 122 Unit Unit (3) +++
FloatingPoint Unit + x/ FPSCR
L1 Push Completed Stores
Vector Permute Unit
Vector Integer er Unit 2
Vector Integer er Unit 1
Vector FPU 128-Bit 128-Bit
32-Bit
32-Bit
32-Bit
Load Miss
64-Bit
64-Bit
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Memory Subsystem L1 Store Queue (LSQ) L1 Load Queue (LLQ) L1 Load Miss (5) L2 Prefetch (3) Instruction Fetch (2) Cacheable Store Request(1) L2 Store Queue (L2SQ) Snoop Push/ L1 Castouts Interventions (4) Bus Accumulator 19-Bit Address 64-Bit Data (8-Bit Parity) External SRAM (1, 2, or 4 Mbytes) 512-Kbyte Unied L2 Cache Controller Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status L3 Cache Controller(1) Line Block 0/1 Tags Status L3CR System Bus Interface Load Queue (11) Bus Store Queue Castout Queue (9)/ Push Queue (10)(2)
L1 Service Queues
Bus Accumulator 36-Bit Address Bus
Notes: 1. The L3 cache interface is not implemented on the PC7447. 2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries. The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
64-Bit Data Bus
3
General Parameters
Table 1 provides a summary of the general parameters of the PC7457. Table 1. Device Parameters
Parameter Technology Die size Transistor count Logic design Packages Core power supply I/O power supply Description 0.13 m CMOS, nine-layer metal 9.1 mm x 10.8 mm 58 million Fully-static PC7447: surface mount 360 ceramic ball grid array (CBGA) PC7457: surface mount 483 ceramic ball grid array (CBGA) 1.3V 500 mV DC nominal or 1.1V 50 mV (nominal, see Table 3 on page 12 1.8V 5% DC, or 2.5V 5% for recommended operating conditions
Features
This section summarizes features of the PC7457 implementation of the PowerPC architecture. Major features of the PC7457 are as follows: * High-performance, superscalar microprocessor - - - - - - - * - As many as 4 instructions can be fetched from the instruction cache at a time As many as 3 instructions can be dispatched to the issue queues at a time As many as 12 instructions can be in the instruction queue (IQ) As many as 16 instructions can be at some stage of execution simultaneously Single-cycle execution for most instructions One instruction per clock cycle throughput for most instructions Seven-stage pipeline control Branch processing unit (BPU) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction - not-taken, strongly not-taken, taken, and strongly taken Up to three outstanding speculative branches Branch instructions that don't update the count register (CTR) or link register (LR) are often removed from the instruction stream Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (BCLR) instructions
Eleven independent execution units and three register files
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- Four integer units (IUs) that share 32 GPRs for integer operands Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from specialpurpose register instructions - Five-stage FPU and a 32-entry FPR file Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Hardware support for denormalized numbers Thirty-two 64-bit FPRs for single- or double-precision operands - Four vector units and 32-entry vector register file (VRs) Vector permute unit (VPU) Vector integer unit 1 (VIU1) handles short-latency AltiVecTM integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for example) Vector floating-point unit (VFPU) - Three-stage load/store unit (LSU) Supports integer, floating-point, and vector instruction load/store traffic Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle throughput Four-cycle FPR load latency (single, double) with one-cycle throughput No additional delay for misaligned access within double-word boundary Dedicated adder calculates effective addresses (EAs) Supports store gathering
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Performs alignment, normalization, and precision conversion for floatingpoint data Executes cache control and TLB instructions Performs alignment, zero padding, and sign extension for integer data Supports hits under misses (multiple outstanding misses) Supports both big- and little-endian modes, including misaligned little-endian accesses * Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: - - - Instructions can be dispatched only from the three lowest IQ entries - IQ0, IQ1, and IQ2 A maximum of three instructions can be dispatched to the issue queues per clock cycle Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue) 16 GPR rename buffers 16 FPR rename buffers 16 VR rename buffers Decode/dispatch stage fully decodes each instruction The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending Guarantees sequential programming model (precise exception model) Monitors all dispatched instructions and retires them in order Tracks unresolved branches and flushes instructions after a mispredicted branch Retires as many as three instructions per clock cycle 32 Kbyte, eight-way set-associative instruction and data caches Pseudo least-recently-used (PLRU) replacement algorithm 32-byte (eight-word) L1 cache block Physically indexed/physical tags Cache write-back or write-through operation programmable on a per-page or per-block basis Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle Caches can be disabled in software Caches can be locked in software
*
Rename buffers - - -
* *
Dispatch unit - - Completion unit
- - - - * - - - - - - - -
Separate on-chip L1 Instruction and data caches (Harvard Architecture)
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- - - - - - MESI data cache coherency maintained in hardware Separate copy of data cache tags for efficient snooping Parity support on cache and tags No snooping of instruction cache except for icbi instruction Data cache supports AltiVec LRU and transient instructions Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding On-chip, 512 Kbyte, eight-way set-associative unified instruction and data cache Fully pipelined to provide 32 bytes per clock cycle to the L1 caches A total nine-cycle load latency for an L1 data cache miss that hits in L2 PLRU replacement algorithm Cache write-back or write-through operation programmable on a per-page or per-block basis 64-byte, two-sectored line size Parity support on cache Provides critical double-word forwarding to the requesting unit Internal L3 cache controller and tags External data SRAMs Support for 1, 2, and 4M bytes (MB) total SRAM space Support for 1 or 2 MB of cache space Cache write-back or write-through operation programmable on a per-page or per-block basis 64-byte (1 MB) or 128-byte (2 MB) sectored line size Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-, or 4-MB of private memory Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst SRAMs Supports parity on cache and tags Configurable core-to-L3 frequency divisors 64-bit external L3 data bus sustains 64-bit per L3 clock cycle 52-bit virtual address; 32- or 36-bit physical address Address translation for 4 Kbyte pages, variable-sized blocks, and 256M bytes segments Memory programmable as write-back/write-through, cachinginhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis Separate IBATs and DBATs (eight each) also defined as SPRs
*
Level 2 (L2) cache interface - - - - - - -
*
Level 3 (L3) cache interface (not implemented on PC7447) - - - - - - - - -
- - - * - - -
Separate memory management units (MMUs) for Instructions and data
-
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Separate instruction and data translation lookaside buffers (TLBs) Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software)
*
Efficient data flow - - - - - - Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2/L3 bus As many as 16 out-of-order transactions can be present on the MPX bus Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache Separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache Hardware-enforced, MESI cache coherency protocols for data cache Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations 1.6V processor core The following three power-saving modes are available to the system: Nap--Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol Sleep--Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled Deep sleep-- When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state
- - *
Multiprocessing support features include the following: - -
*
Power and thermal management - -
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Thermal management facility provides software-controllable thermal management. Thermal management is performed through the use of three supervisor-level registers and a PC7457-specific thermal management exception Instruction cache throttling provides control of instruction fetching to limit power consumption
- * * *
Performance monitor can be used to help debug system designs and improve software efficiency In-system testability and debugging features through JTAG boundary-scan capability Testability - - - LSSD scan design IEEE 1149.1 JTAG interface Array built-in self test (ABIST) - factory test only Parity checking on system bus and L3 cache bus Parity checking on the L2 and L3 cache tag arrays
*
Reliability and serviceability - -
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Signal Description
Figure 2. PC7457 Microprocessor Signal Groups
18 64 BR Address Arbitration BG 1 1 8 1 2 A[0:35] Address Transfer AP[0:4] 36 5 4 2 L3_ADDR[17:0](1) L3-DATA[0:63] L3_DP[0:7] L3_VSEL L3_CLK[0:1] L3_ECHO_CLK[0:3] L3_CNTL[0:1] L3 Cache Clock/Control L3 Cache Address/Data Note: L3 cache interface is not supported in the PC7441, PC7445, or the PC7447
TS TT[0:4] TBST Address Transfer Attributes TSIZ[0:2] GBL WT CI
1 5 1 3 1 1 1 PC7457
1 1 1 1 1 1 1 1
INT SMI MCP SRESET HRESET CKSTP_IN CKSTP_OUT TBEN QREQ QACK BVSEL BMODE[0:1] PMON_IN PMON_OUT SYSCLK PLL_CFG[0:3](2) PLL_EXT EXT_QUAL CLK_OUT TCK TDI TDO TMS TRST AVDD GND Test Interface (JTAG) Clock Control Processor Status/Control Interrupts/Resets
AACK Address Transfer Termination ARTRY SHD0/SHD1 HIT
1 1 2 1
1 1 1 2 1
DBG Data Arbitration DTI[0:3] DRDY
1 4 1
1 1 4 1
D[0:63] Data Transfer DP[0:7]
64 8
1 1 1
Data Transfer Termination
TA TEA
1 1
1 1 1 1
VDD OVDD GVDD
Notes:
1. For the PC7457, there are 19 L3_ADDR signals, (L3_ADDR[0:18]. 2. For the PC7447 and PM7457, there are 5 PLL_CFG signals, (PLL_CFG[0:4].
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Detailed Specification Scope Applicable Documents Requirements
General Design and Construction
Terminal Connections Depending on the package, the terminal connections are as shown in Table 16, Table 3 and Figure 2. The microcircuits are in accordance with the applicable documents and as specified herein. This specification describes the specific requirements for the microprocessor PC7457 in compliance with Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings(1)
Symbol VDD
(2) (2)
Characteristic Core supply voltage PLL supply voltage BVSEL = 0 Processor bus supply voltage BVSEL = HRESET or OVDD L3VSEL = HRESET L3 bus supply voltage L3VSEL = 0 L3VSEL = HRESET or GVDD Processor bus Input voltage L3 bus JTAG signals Storage temperature range
Maximum Value -0.3 to 1.60 -0.3 to 1.60 -0.3 to 1.95 -0.3 to 2.7 -0.3 to 1.65 -0.3 to 1.95 -0.3 to 2.7 -0.3 to OVDD + 0.3 -0.3 to GVDD + 0.3 -0.3 to OVDD + 0.3 -55 to 150
Unit V V V V V V V V V V C
AVDD
OVDD(3)(4) OVDD(3)(5) GVDD GVDD
(3)(6) (3)(7)
GVDD(3)(8) VIN(9)(10) VIN VIN TSTG Notes:
(9)(10)
1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. BVSEL must be set to 0, such that the bus is in 1.8V mode. 5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode. 6. L3VSEL must be set to HRESET (inverse of HRESET), such that the bus is in 1.5V mode.
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7. L3VSEL must be set to 0, such that the bus is in 1.8V mode. 8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode. 9. Caution: VIN must not exceed OVDD or GVDD by more than 0.3V at any time including during power-on reset. 10. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
Recommended Operating Conditions
Table 3. Recommended Operating Conditions(1)
Recommended Value Symbol VDD AVDD
(2)
Characteristic Core supply voltage PLL supply voltage BVSEL = 0 Processor bus supply voltage BVSEL = HRESET or OVDD L3VSEL = 0 L3 bus supply voltage L3VSEL = HRESET or GVDD L3VSEL = HRESET Processor bus Input voltage L3 bus JTAG signals Die-junction temperature
Min
Max
Unit V V V V V V V
1.3V 50 mV or 1.1V 50 mV 1.3V 50 mV or 1.1V 50 mV 1.8V 5% 2.5V 5% 1.8V 5% 2.5V 5% 1.5V 5% GND GND GND -55 OVDD GVDD OVDD 125
OVDD OVDD GVDD GVDD GVDD(3) VIN VIN VIN Tj Notes:
V V V
C
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. This voltage is the input to the filter discussed in Section "PLL Power Supply Filtering" on page 54 and not necessarily the voltage at the AVDD pin which may be reduced from VDD by the filter. 3. HRESET is the inverse of HRESET.
Figure 3. Overshoot/Undershoot Voltage
OVDD/GVDD + 20% OVDD/GVDD + 5% OVDD/GVDD
VIH
VIL GND GND - 0.3V GND - 0.7V Not to exceed 10% of tSYSCLK
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The PC7457 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7457 core voltage must always be provided at nominal 1.3V (see Table 3 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 4. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins. Table 4. Input Threshold Voltage Setting
BVSEL Signal 0 HRESET HRESET 1 Notes: Processor Bus Input Threshold is Relative to: 1.8V Not available 2.5V 2.5V L3VSEL Signal(1) 0 HRESET HRESET 1 L3 Bus Input Threshold is Relative to: 1.8V 1.5V 2.5V 2.5V Notes
(2)(3)(5) (2)(4)(5) (2) (2)
1. Not implemented on PC7447. 2. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2. 3. If used, pull-down resistors should be less than 250 4. Applicable to L3 bus interface only. HRESET is the inverse of HRESET. 5. 1.8V I/O mode and 1.5V I/O mode are not supported in N spec at VDD = 1.1V.
Thermal Characteristics
Package Characteristics Table 5. Package Thermal Characteristics(1)
Value Symbol RJA(2)(3) RJMA(2)(4) RJMA(2)(4) RJMA(2)(4) RJB(5) RJC Notes:
(6)
Characteristic Junction-to-ambient thermal resistance, natural convection Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board Junction-to-board thermal resistance Junction-to-case thermal resistance
PC7447 22 14 16 11 6 < 0.1
PC7457 20 14 15 11 6 < 0.1
Unit
C/W C/W C/W C/W C/W C/W
1. See "Thermal Management Information" on page 15 for more details about thermal management. 2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RJC for the part is less than 0.1C/W.
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Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 4 on page 13, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance The die junction-to-ball thermal resistance
Figure 33 on page 58 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Printed-Circuit Board Die/Package Die Junction Package/Leads
External Resistance
Radiation
Convection
Note the internal versus external package resistance. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms.
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Thermal Management Information This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design - the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods - spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see Figure 32 on page 55); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. If a spring clip is used, the spring force should not exceed 10 pounds. Figure 5. Package Exploded Cross-sectional View with Several Heat Sink Options
Heat Sink CBGA Package
Heat Sink Clip
Thermal Interface Material
Printed-Circuit Board
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Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 5 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 32 on page 55). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure and is recommended due to the high power dissipation of the PC7457. Of course, the selection of any thermal interface material depends on many factors - thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. Figure 6. Thermal Performance of Select Thermal Interface Material
2 Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
1.5
1
0.5
0 0 10 20 30 40 50 60 70 80
Contact Pressure (psi)
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = TI + Tr + (RJC + Rint + Rsa) x Pd where: Tj is the die-junction temperature TI is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet
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RJC is the junction-to-case thermal resistance Rint is the adhesive or interface material thermal resistance Rsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3 on page 12. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (R int ) is typically about 1.5C/W. For example, assuming a Ta of 30C, a Tr of 5C, a CBGA package RJC = 0.1, and a typical power consumption (Pd) of 18.7W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30C + 5C + (0.1C/W + 1.5C/W + sa) x 18.7W For this example, a Rsa value of 2.1C/W or less is required to maintain the die junction temperature below the maximum value of Table 3 on page 12. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature - airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. For system thermal modeling, the PC7447 and PC7457 thermal model is shown in Figure 4 on page 14. Four volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are modeled using the package outline size of the package. The other two, die, and bump and underfill, have the same size as the die. The silicon die should be modeled 9.64 x 11 x 0.74 mm with the heat source applied as a uniform source at the bottom of the volume. The bump and underfill layer is modeled as 9.64 x 11 x 0.69 mm (or as a collapsed volume) with orthotropic material properties: 0.6W/(m x K) in the xy-plane and 2W/(m x K) in the direction of the z-axis. The substrate volume is 25 x 25 x 1.2 mm (PC7447) or 29 x 29 x 1.2 mm (PC7457), and this volume has 18W/(m x K) isotropic conductivity. The solder ball and air layer is modeled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can also be modeled as a collapsed volume using orthotropic material properties: 0.034W/(m x K) in the xy-plane direction and 3.8W/(m x K) in the direction of the z-axis.
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Figure 7. Recommended Thermal Model of PC7447 and PC7457
Die z Conductivity Value Bump and Underfill kx ky kz Substrate k 18 Solder Ball and Air Die kx ky kz 0.034 0.034 3.8 y Side View of Model (Not to Scale) Substrate 0.6 0.6 2 W/(m x K) Unit Substrate Solder and Air Side View of Model (Not to Scale) x Bump and Underfill
Power Consumption Table 6. Power Consumption for PC7457
Processor (CPU) Frequency Full-Power Mode Core Power Supply Typical(1)(2) Maximum(1)(3) Nap Mode Typical(1)(2) Sleep Mode Typical(1)(2) 1.2 1.2 5.1 5.1 W 1.3 1.3 5.2 5.2 W 600 MHz 1.1 5.3 7.9 1000 MHz 1.1 8.3 11.5 1000 MHz 1.3 15.8 22.0 1200 MHz 1.3 17.5 24.2 W W Unit
Deep Sleep Mode (PLL Disabled) Typical(1)(2) Notes: 1.1 1.1 5.0 5.0 W
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically < 5% of VDD power. Worst case power consumption for AVDD < 3 mW 2. Typical power is an average value measured at the nominal recommended VDD (see Table 3 on page 12) and 65 C while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
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3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 3 on page 12) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 4. Doze mode is not a user-definable state; it is an intermediate state between fullpower and either nap or sleep mode. As a result, power consumption for this mode is not tested.
Electrical Characteristics
Static Characteristics
Table 7 provides the DC electrical characteristics for the PC7457. Table 7. DC Electrical Specifications (see Table 3 on page 12 for Recommended Operating Conditions)
Symbol VIH(2) VIH VIH VIL(2)(6) VIL VIL IIN(2)(3) ITSI(2)(3)(4) VOH(6) VOH VOH VOL(6) VOL VOL CIN Notes: 1. 2. 3. 4. Capacitance, VIN = 0V, f = 1 MHz L3 interface
(5)
Characteristic
Nominal Bus Voltage(1) 1.5
Min GVDD x 0.65 OVDD/GVDD x 0.65 1.7 -0.3 -0.3 -0.3 - - OVDD/GVDD - 0.45 OVDD/GVDD - 0.45 1.8 - - - -
Max GVDD + 0.3 OVDD/GVDD + 0.3 OVDD/GVDD + 0.3 GVDD x 0.35 OVDD/GVDD x 0.35 0.7 30 30 - - - 0.45 0.45 0.6 9.5 8.0
Unit V V V V V V A A V V V V V V pF pF
Input high voltage (all inputs including SYSCLK)
1.8 2.5 1.5
Input low voltage (all inputs including SYSCLK)
1.8 2.5
Input leakage current, VIN = GVDD/OVDD High-impedance (off-state) Leakage current, VIN = GVDD/OVDD
- - 1.5
Output high voltage, IOH = -5 mA
1.8 2.5 1.5
Output low voltage, IOL = 5 mA
1.8 2.5 -
All other inputs(5)
-
Nominal voltages; see Table 3 on page 12 for recommended operating conditions. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or -5%). 5. Capacitance is periodically sampled rather than 100% tested. 6. Applicable to L3 bus interface only
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Dynamic Characteristics
This section provides the AC electrical characteristics for the PC7457. After fabrication, functional parts are sorted by maximum processor core frequency as shown in section "Clock AC Specifications" and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core frequency; See "Ordering Information" on page 59. Table 8 provides the clock AC timing specifications as defined in Figure 8 and represents the tested operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8 is considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in Table 8.
Clock AC Specifications
Table 8. Clock AC Timing Specifications (See Table 3 on page 12 for Recommended Operating Conditions)
Maximum Processor Core Frequency 600 MHz VDD = 1.1V Symbol fCORE(1) fVCO(1) fSYSCLK tSYSCLK
(1)(2) (2)
867 MHz VDD = 1.1V Min 500 1000 33 6 - 40 - - Max 867 1733 167 30 1 60 150 100
1000 MHz VDD = 1.1V Min 500 1000 33 6 - - - - Max 1000 2000 167 30 1 - - - Unit MHz MHz MHz ns ns % ps s
Characteristic Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter
(5)(6) (7)
Min 500 1000 33 6 - 40 - -
Max 600 1200 167 30 1 60 150 100
tKR, tKF(3) tKHKL/tSYSCLK(4)
Internal PLL relock time
Maximum Processor Core Frequency 867 MHz VDD = 1.3V Symbol fCORE(1) fVCO
(1) (1)(2)
1000 MHz VDD = 1.3V Min 600 1200 33 6 - 40 - - Max 1000 2000 167 30 1 60 150 100
1200 MHz VDD = 1.3V Min 600 1200 33 6 - 40 - - Max 1200 2400 167 30 1 60 150 100
1267 MHz VDD = 1.3V Min 600 1200 33 6 - 40 - - Max 1267 2534 167 30 1 60 150 100 Unit MHz MHz MHz ns ns % ps s
Characteristic Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter(5)(6) Internal PLL relock time
(7)
Min 600 1200 33 6 - 40 - -
Max 867 1733 167 30 1 60 150 100
fSYSCLK
tSYSCLK(2) tKR, tKF(3) tKHKL/ tSYSCLK(4)
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Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency and PLL (VCO) frequency don't exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in "PLL Configuration" on page 51 for valid PLL_CFG[0:4] settings 2. Assumes lightly-loaded, single-processor system. 3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V. 4. Timing is guaranteed by design and characterization. 5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design. 6. The SYSCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter. 7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 8 provides the SYSCLK input timing diagram. Figure 8. SYSCLK Input Timing Diagram
SYSCLK VM tKHKL tSYSCLK VM VM CV IL CVIH
tKR
tKF
VM = Midpoint Voltage (OVDD/2)
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Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the PC7457 as defined in Figure 17 on page 34 and Figure 9 on page 23. Timing specifications for the L3 bus are provided in section "L3 Clock AC Specifications" on page 24.
Table 9. Processor Bus AC Timing Specifications(1) (at Recommended Operating Conditions, see Table 3 on page 12.)
All Speed Grades Symbol(2) tAVKH tDVKH tIVKH Parameter Input setup times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL Input hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL Output valid times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], TS, SHD[0:1], WT Output hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], TS, SHD[0:1], WT SYSCLK to output enable SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) SYSCLK to TS high impedance after precharge Maximum delay to ARTRY/SHD0/SHD1 precharge SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge VDD = 1.1V 2.0 2.0 2.0 Min VDD = 1.3V 1.8 1.8 1.8 Max - - - Unit
ns
tMVKH(8) tAXKH tDXKH tIXKH
2 0 0 0
1.8 0 0 0
- - - -
ns
tMXKH(8) tKHAV tKHDV tKHOV
0 - - -
0 - - -
- 2 2 2
ns
tKHAX tKHDX tKHOX
0.5 0.5 0.5
0.5 0.5 0.5
- - -
ns
tKHOE tKHOZ tKHTSPZ(3)(4)(5) tKHARP(3)(5)(6)(7) tKHARPZ(3)(5)(6)(7) Notes:
0.5 - - - -
0.5 - - - -
- 3.5 1 1 2
ns ns tSYSCLK tSYSCLK tSYSCLK
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50 load (see Figure 17 on page 34). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
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2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high before returning to high impedance as shown in Figure 10 on page 24. The nominal precharge width for TS is 0.5 x tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design. 5. Guaranteed by design and not tested. 6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 10 on page 24 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design. 7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations). 8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These inputs must remain stable after the second sample. See Figure 9 on page 23 for sample timing.
Figure 9. Mode Input Timing Diagram
HRESET tMVRH tMXRH Mode Signals VM
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Figure 10 provides the input/output timing diagram for the PC7457. Figure 10. Input/Output Timing Diagram
SYSCLK VM tAVKH tIVKH All Inputs tKHAV tKHDV tKHOV tKHAX tKHDX tKHOX VM tAXKH tIXKH VM
All Outputs (Except TS, ARTRY, SHD0, SHD1) tKHOE All Outputs (Except TS, ARTRY, SHD0, SHD1)
tKHOZ
tKHTSPZ tKHTSV tKHTSX tKHTSV TS tKHARPZ tKHARV ARTRY, SHD0, SHD1 tKHARP tKHARX
Note:
VM = Midpoint Voltage (OVDD/2)
L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divisor ratio. See Table 18 on page 51 for example core and L3 frequencies at various divisors. Table 10 on page 25 provides the potential range of L3_CLK output AC timing specifications as defined in Figure 11 on page 25. The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies available in the PC7457, however, most SRAM designs will be not be able to operate in this mode using current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is considered to be the practical maximum in a typical system. The maximum L3_CLK frequency for any application of the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the SRAM, bus loading, and printed-circuit board trace length, and may be greater or less than the value given in Table 10. Note that SYSCLK input jitter and L3_CLK[0:1] output jitter are already comprehended in the L3 bus AC timing specifications and do not need to be separately accounted for in an L3 AC timing analysis. Clock skews, where applicable, do need to be accounted for in an AC timing analysis.
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Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a socketed part on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 250 MHz or lower. Table 10. L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see Table 3 on page 12)
All Speed Grades Symbol fL3_CLK(1) tL3_CLK(1) tCHCL/tL3_CLK(2) tL3CSKW1
(3)
Parameter L3 clock frequency L3 clock cycle time L3 clock duty cycle L3 clock output-to-output skew (L3_CLK0 to L3_CLK1) L3 clock output-to-output skew (L3_CLK[0:1] to L3_ECHO_CLK[1:3]) L3 clock jitter(5)
Min - - - - - -
Typical 200 5 50 - - -
Max
Unit MHz
- - 100 100 75
ns % ps ps ps
tL3CSKW2(4) Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See "L3 Clock AC Specifications" on page 24 for an explanation that this maximum frequency is not functionally tested at speed by Motorola. The minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively. 2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage. 3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals which are common to both SRAM chips in the L3. 4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1. 5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data and control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3 timing analysis.
Figure 11. L3_CLK_OUT Output Timing Diagram
tL3_CLK tCHCL L3_CLK0 VM VM VM tL3CR tL3CF
L3_CLK1
VM
VM
VM
VM tL3CSKW1
For PB2 or Late Write: L3_ECHO_CLK1
VM
VM
VM
VM tL3CSKW2
L3_ECHO_CLK3
VM
VM
VM
VM tL3CSKW2
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L3 Bus AC Specifications
The PC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate (DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is programmed in L3CR[22:23] and the PC7457 then follows the appropriate protocol for that type. The designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some observations about the L3 interface. * * * * * The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched For 1M byte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB) For 2M bytes of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB) No pull-up resistors are required for the L3 interface For high speed operations, L3 interface address and control signals should be a "T" with minimal stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 12 shows the AC test load for the L3 interface.
Figure 12. AC Test Load for the L3 Interface
Output
Z0 = 50 RL = 50 OVDD/2
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal reflection, there is a high probability that the AC timing of the PC7457 L3 interface will meet the maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic, guard-banded AC specifications (see Table 12 on page 28, Table 13 on page 29, and Table 14 on page 32), the limitations of functional testers described in Section "L3 Clock AC Specifications" on page 24 and the uncertainty of clocks and signals which inevitably make worst-case critical path timing analysis pessimistic. More specifically, certain signals within groups should be delay-matched with others in the same group while intergroup routing is less critical. Only the address and control signals are common to both SRAMs and additional timing margin is available for these signals. The double-clocked data signals are grouped with individual clocks as shown in Figure 13 on page 30 or Figure 15 on page 33, depending on the type of SRAM. For example, for the MSUG2 DDR SRAM (see Figure 13); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely coupled group of outputs from the PC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely coupled group of inputs. The PC7450 RISC Microprocessor Family User's Manual refers to logical settings called "sample points" used in the synchronization of reads from the receive FIFO. The computation of the correct value for this setting is system-dependent and is described in the PC7450 RISC Microprocessor Family User's Manual. Three specifications are used in this calculation and are given in Table 11 on page 27. It is essential that all three specifications are included in the calculations to determine the sample points as incorrect settings can result in errors and unpredictable behavior. For more information, see the PC7450 RISC Microprocessor Family User's Manual.
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Table 11. Sample Points Calculation Parameters
Symbol tAC tCO tECI Notes: Parameter Delay from processor clock to internal_L3_CLK
(1)
Max 3/4 3 3
Unit tL3_CLK ns ns
Delay from internal_L3_CLK to L3_CLK[n] output pins(2) Delay from L3_ECHO_CLK[n] to receive latch(3)
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at the SRAM within a valid address window and provide adequate setup and hold time. This offset is reflected in the L3 bus interface AC timing specifications, but must also be separately accounted for in the calculation of sample points and, thus, is specified here. 2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling edge at the L3CLK[n] pins. 3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be sampled from the FIFO.
Effects of L3OHCR Settings on L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR). Each field controls the timing for a group of signals. The AC timing specifications presented herein represent the AC timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the associated signals, increasing the output valid time and hold time of the affected signals. In the special case of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold times of all signals being latched relative to that clock signal. The amount of delay added is summarized in Table 12 on page 28. Note that these settings affect output timing parameters only and don't impact input timing parameters of the L3 bus in any way.
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Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
Output Valid Time Field name(1) Affected Signals Value 0b00 L3AOH L3_ADDR[18:0], L3_CNTL[0:1] 0b01 0b10 0b11 0b000 0b001 0b010 L3CLKn_OH All signals latched by SRAM connected to L3_CLKn 0b011 0b100 0b101 0b110 0b111 0b000 0b001 0b010 L3DOHn L3_DATA[n:n + 7], L3_DP[n/8] 0b011 0b100 0b101 0b111 0b111 Notes: 1. 2. 3. 4. 5.
t t t
Output Hold Time Parameter Symbol(2) Change(3) 0
t
Parameter Symbol(2)
Change(3) 0 +50 +100 +150 0 -50
Unit
Notes
(4)
+50 +100 +150 0 -50 -100
(4) (5) (5) (5) (5) (5)
L3CHOV
L3CHOX
L3CHOV L3CHDV L3CLDV
-100 -150 -200 -250 -300 -350 0 +50 +100
t t
t
L3CHOX L3CHDX L3CLDX
-150 -200 -250 ps -300 -350 0 +50 +100
t
t
(5) (5) (4)
L3CHDV L3CLDV
+150 +200 +250 +350 +350
t
L3CHDX L3CLDX
+150 +200 +250 +350 +350
t
t
Refer to the PC7450 RISC Microprocessor Family User's Manual for specific information regarding L3OHCR. See Table 13 on page 29 and Table 14 on page 32 for more information. Guaranteed by design; not tested or characterized. Default value. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of all signals latched relative to that clock signal by the SRAM; see Figure 13 on page 30 and Figure 15 on page 33.
L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 13. Outputs from the PC7457 are actually launched on the edges of an internal clock phasealigned to SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock output with 90 phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control, data, and L3_CLKn signals have propagated across the printed-wiring board. Inputs to the PC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs.
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These CQ clocks are received on the L3_ECHO_CLKn inputs of the PC7457. An internal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal receiving latches. This delayed clock is used to capture the data into these latches which comprise the receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently read out of the FIFO synchronously to the processor clock. The time between writing and reading the data is set by using the sample point settings defined in the L3CR register. Table 13 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 13, assuming the timing relationships shown in Figure 14 and the loading shown in Figure 12 on page 26. Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions (see Table 3 on page 12)
All Speed Grades Symbol tL3CR, tL3CF tL3DVEH, tL3DVEL tL3DXEH, tL3DXEL tL3CHDV, tL3CLDV tL3CHOV tL3CHDX, tL3CLDX tL3CHOX tL3CLDZ Notes: Parameter L3_CLK rise and fall time
(1) (2)(3)(4)
Min - -0.35 2.1 - -
(5)(6)(7)(8)
Max 0.75 - - (-tL3CLK/4) + 0.60 (tL3CLK/4) + 0.65 - - TBD
Unit ns ns ns ns ns ns ns ns
Setup times: Data and parity
Input hold times: Data and parity(2)(4) Valid times: Data and parity(5)(6)(7)(8) Valid times: All other outputs
(5)(7)(8)
Output hold times: Data and parity
(tL3CLK/4) - 0.60 (tL3CLK/4) - 0.50 -
Output hold times: All other outputs(5)(7)(8) L3_CLK to high impedance: Data and parity
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins. 3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 14. For consistency with other input setup time specifications, this will be treated as negative input setup time. 4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency. 5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 12 on page 26). 6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 14 on page 31. For consistency with other output valid time specifications, this will be treated as negative output valid time. 7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 8. Assumes default value of L3OHCR. See "Effects of L3OHCR Settings on L3 Bus AC Specifications" on page 27 for more information.
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Figure 13 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs. Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface
PC7457 L3ADDR[18:0] L3_CNTL[0] L3_CNTL[1] Denotes Receive (SRAM to PC7457) Aligned Signals L3_ECHO_CLK[0] {L3DATA[0:15], L3DP[0:1]} L3_CLK[0] {L3DATA[16:31], L3DP[2:3]} L3_ECHO_CLK[1] Denotes Transmit (PC7457 to SRAM) Aligned Signals SRAM 0 SA[18:0] B1 B2 CQ D[0:17] CK D[18:35] CQ SRAM 1 SA[18:0] B1 B2 L3ECHO_CLK[2] {L3DATA[32:47], L3DP[4:5]} L3_CLK[1] {L3DATA[48:63], L3DP[6:7]} L3_ECHO_CLK[3] CQ D[0:17] CK D[18:35] CQ G LBO CQ CQ CK GND GND NC NC GVDD/2 (1)
B3
GND
B3 G LBO CQ CQ CK
GND GND GND NC NC GVDD/2 (1)
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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Figure 14 shows the L3 bus timing diagrams for the PC7457 interfaced to MSUG2 SRAMs. Figure 14. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
Outputs L3_CLK[0,1] VM tL3CHOV VM tL3CHOZ tL3CHOX ADDR, L3CNTL tL3CLDV tL3CHDV L3DATA WRITE tL3CHDX tL3CLDX tL3CLDZ VM VM VM
Note:
tL3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be time before the clock edge.
Inputs L3_ECHO_CLK[0,1,2,3] VM VM VM VM tL3DXEL VM
tL3DVEL tL3DVEH L3 Data and Data Parity Inputs tL3DXEH
Notes:
1. tL3DVEH and tL3DVEL as drawn here will be negative numbers, that is, input setup time will be time after the clock edge. 2. VM = Midpoint Voltage (GVDD/2)
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L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in Figure 15 on page 33. These SRAMs are synchronous to the PC7457; one L3_CLKn signal is output to each SRAM to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed L3_CLKn signal it received. The PC7457 needs a copy of that delayed clock which launched the SRAM read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock received at the SRAMs. The PC7457 will latch the incoming data on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2. Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 15, assuming the timing relationships of Figure 16 and the loading of Figure 12 on page 26.
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Conditions (see Table 3 on page 12)
All Speed Grades Symbol tL3CR, tL3CF tL3DVEH tL3DXEH tL3CHDV tL3CHOV tL3CHDX tL3CHOX tL3CHDZ tL3CHOZ Notes: Parameter L3_CLK rise and fall time
(1)(2) (2)(3)
Min - 0.1 - - -
(2)(4)(5)(6)
Max 0.75 - 0.7 2.5 1.8 - - 3.0 3.0
Unit ns ns ns ns ns ns ns ns ns
Setup times: Data and parity
Input hold times: Data and parity(2)(3) Valid times: Data and parity(2)(4)(5)(6) Valid times: All other outputs
(5)(6)
Output hold times: Data and parity
1.4 1.0 - -
Output hold times: All other outputs(2)(5)(6) L3_CLK to high impedance: Data and parity(2) L3_CLK to high impedance: All other outputs
(2)
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. Timing behavior and characterization are currently being evaluated. 3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins. 4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 14). 5. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 6. Assumes default value of L3OHCR. See "Effects of L3OHCR Settings on L3 Bus AC Specifications" on page 27 for more information.
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Figure 15 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs. Figure 15. Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface
PC7457 L3_ADDR[16:0] L3_CNTL[0] L3_CNTL[1] Denotes Receive (SRAM to PC7457) Aligned Signals L3_ECHO_CLK[0] {L3_DATA[0:15], L3_DP[0:1]} L3_CLK[0] {L3_DATA[16:31], L3_DP[2:3]} L3_ECHO_CLK[1] Denotes Transmit (PC7457 to SRAM) Aligned Signals L3_ECHO_CLK[2] {L3_DATA[32:47], L3_DP[4:5]} DQ[0:17] L3_CLK[1] {L3_DATA[48:63], L3_DP[6:7]} L3_ECHO_CLK[3] K DQ[18:36] SRAM 1 SA[16:0] SS SW DQ[0:17] K DQ[18:36 ] ZZ G K GND GND GVDD/2 (1) SRAM 0 SA[16:0] SS SW
ZZ G K
GND GND GVDD/2 (1)
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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Figure 16 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs. Figure 16. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
Outputs L3_CLK[0,1] L3_ECHO_CLK[1,3] tL3CHOV ADDR, L3_CNTL tL3CHOZ tL3CHDV L3DATA WRITE tL3CHDZ Inputs L3_ECHO_CLK[0,2] VM tL3DVEH tL3DXEH Parity Inputs L3 Data and Data tL3CHDX VM VM tL3CHOX
Note:
VM = Midpoint Voltage (GVDD/2)
Figure 17. AC Test Load
Output
Z0 = 50 RL = 50 OVDD/2
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IEEE 1149.1 AC Timing Specifications Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 19 through Figure 22 on page 37.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)(1)at Recommended Operating Conditions (see Table 3 on page 12)
Symbol fTCLK tTCLK tJHJL tJR and tJF tTRST(2) tDVJH tIVJH
(3)
Parameter TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.4V TCK rise and fall times TRST assert time Input Setup Times: Boundary-scan data TMS, TDI Input Hold Times: Boundary-scan data TMS, TDI Valid Times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO TCK to output high impedance: Boundary-scan data TDO
Min 0 30 15 0 25 4 0 20 25 4 4 TBD TBD
Max 33.3 - - 2 - - - - - 20 25 TBD TBD
Unit MHz ns ns ns ns ns
tDXJH(3) tIXJH tJLDV(4) tJLOV tJLDX(4) tJLOX tJLDZ(4)(5) tJLOZ Notes:
ns
ns
3 3
19 9
ns
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 18). Time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC7457. Figure 18. Alternate AC Test Load for the JTAG Interface
Output Z0 = 50 RL = 50 OVDD/2
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Figure 19. JTAG Clock Input Timing Diagram
TCLK VM tJHJL tTCLK VM VM tJR tJF
Note:
VM = Midpoint Voltage (OVDD/2)
Figure 20. TRST Timing Diagram
VM
TRST tTRST
VM
Note:
VM = Midpoint Voltage (OVDD/2)
Figure 21. Boundary-scan Timing Diagram
TCK VM tDVJH tDXJH Boundary Data Inputs tJLDV tJLDX Boundary Data Outputs Output Data Valid Input Data Valid VM
tJLDZ Boundary Data Outputs Output Data Valid
Note:
VM = Midpoint Voltage (OVDD/2)
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Figure 22. Test Access Port Timing Diagram
TCK VM tIVJH TDI, TMS tJLOV tJLOX TDO Output Data Valid Input Data Valid VM
tIXJH
tJLOZ TDO Output Data Valid
Note:
VM = Midpoint Voltage (OVDD/2)
Preparation for Delivery Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: * * * * * * Devices should be handled on benches with conductive and grounded surfaces. Ground test equipment, tools and operator. Do not handle devices by the leads. Store devices in conductive foam or carriers. Avoid use of plastic, rubber or silk in MOS areas. Maintain relative humidity above 50% if practical.
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Package Mechanical Data
Package Parameters for the PC7447, 360 CBGA
The following sections provide the package parameters and mechanical dimensions for the CBGA package. The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 mm x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.72 mm 3.24 mm 0.89 mm (35 mil)
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Pin Assignment
Figure 23 shows the pinout of the PC7447, 360 CBGA package as viewed from the top surface. Figure 24 shows the side profile of the CBGA package to indicate the direction of the top surface view. Figure 23. Pinout of the PC7447, 360 CBGA Package as Viewed from the Top Surface
1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 24. Side View of the CBGA Package
Substrate Assembly Encapsulant View Die
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Pinout Listings
Table 16 provides the pinout listing for the PC7447, 360 CBGA package. Table 15 provides the pinout listing for the PC7457, 483 CBGA package.
Note: This pinout is not compatible with the PC750, PC7400, or PC7410 360 BGA package. I/F Select(1) BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
Table 16. Pinout Listing for the PC7447, 360 CBGA Package
Signal Name A[0:35](2) AACK AP[0:4] ARTRY AVDD BG BMODE0(4) BMODE1 BR BVSEL(1)(6) CI(3) CKSTP_IN CKSTP_OUT CLK_OUT
(5) (3)
Pin Number E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1, B12, C4, G10, B11 R1 C1, E3, H6, F5, G7 N2 A8 M1 G9 F8 D2 B7 J1 A3 B1 H2 R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9, P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17, W3, V17, U4, U8, U7, R7, P6, R8, W8, T8 M2 T3, W4, T4, W9, M6, V3, N8, W6 R3 G1, K1, P1, N1
Active High Low High Low - Low Low Low Low High Low Low Low High
I/O I/O Input I/O I/O Input Input Input Input Output Input Output Input Output Output
D[0:63]
High
I/O
BVSEL
DBG DP[0:7] DRDY
(7)
Low High Low High High Low
Input I/O Output Input Input I/O
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
DTI[0:3](8) EXT_QUAL GBL
(9)
A11 E2 B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10, J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13, N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11, V15 B2 D8 D4 G8 B3
GND
-
-
N/A
HIT(7) HRESET INT L1_TSTCLK(9) L2_TSTCLK
(10)
Low Low Low High High
Output Input Input Input Input
BVSEL BVSEL BVSEL BVSEL BVSEL
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Table 16. Pinout Listing for the PC7447, 360 CBGA Package (Continued)
Signal Name Pin Number A6, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15, B16, B17, B18, B19, C13, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17, D18, D19, E12, E13, E14, E15, E16, E19, F12, F13, F14, F15, F16, F17, F18, F19, G11, G12, G13, G14, G15, G16, G19, H14, H15, H16, H17, H18, H19, J14, J15, J16, J17, J18, J19, K15, K16, K17, K18, K19, L14, L15, L16, L17, L18, L19, M14, M15, M16, M17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19, P15, P16, P18, P19 E8 C9 B4, C2, C12, D5, E18, F2, G18, H3, J5, K2, L5, M3, N6, P2, P8, P11, R4, R13, R16, T6, T9, U2, U12, U16, V4, V7, V10, V14 B8, C8, C7, D7, A7 D9 A9 G5 P4
(3)
Active
I/O
I/F Select(1)
No Connect(11)
-
-
-
LSSD_MODE(6)(12) MCP OVDD PLL_CFG[0:4] PMON_IN
(13)
Low Low - High Low Low Low Low Low Low Low - Low High Low High High High Low - - High Low Low High High Low -
Input Input - Input Input Output Input Output I/O Input Input Input Input Input Output Input Input Output Input Input Input Input Input I/O Output I/O Output -
BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL N/A
PMON_OUT QACK QREQ SHD[0:1] SMI SRESET SYSCLK TA TBEN TBST TCK TDI
(6)
E4, H5 F9 A2 A10 K6 E1 F11 C6 B9 A4 L1
TDO TEA TEST[0:3] TEST[4] TMS(6) TRST(6)(14) TS
(3) (12)
A12, B6, B10, E10 D10 F1 A5 L4 G6, F7, E7 E5, E6, F6, E9, C5 D3 H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13, M8, M10, M12
(9)
TSIZ[0:2] TT[0:4] WT(3) VDD
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Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, the pull-down resistor should be less than 250. For actual recommended value of VIN or supply voltages see Figure 3 on page 12. 2. Unused address pins must be pulled down to GND. 3. These pins require weak pull-up resistors (for example, 4.7 k) to maintain the control signals in the negated state after they have been actively negated and released by the PC7447 and other bus masters. 4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going high. 5. This signal must be negated during reset, by pull up to OVDD or negation by HRESET (inverse of HRESET), to ensure proper operation. 6. Internal pull up on die. 7. Ignored in 60x bus mode. 8. These signals must be pulled down to GND if unused, or if the PC7447 is in 60x bus mode. 9. These input signals are for factory use only and must be pulled down to GND for normal machine operation. 10. It is recommended this test signal be tied to HRESET; however, other configurations will not adversely affect performance. 11. These signals are for factory use only and must be left unconnected for normal machine operation. 12. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation. 13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software. 14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation
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Mechanical Dimensions for the PC7447, 360 CBGA
Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7447, 360 CBGA package. Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7447, 360 CBGA Package
2X 0.2 D D1 D2 0.15 A 1 A B Capacitor Region
D3 A1 CORNER
E3 E E2 E1 E4
Millimeters DIM A A1 A2 A3 b D D1 MIN 2.72 0.80 1.10 - 0.82 25 BSC - 8 - 10.9 1.27 BSC 25 BSC - 8 - 9.55 11.3 - 6.5 9.75 11.3 - 6.5 11.1 MAX 3.20 1 1.30 0.6 0.93
2X 0.2 C 1 2 3 4 5 6 7 8 9 10111213141516 1718 19 W V U T R P N M L K J H G F E D C B A D4
D2 D3 D4 e E E1 E2 E3 E4 A3
A2 A1 A 0.35 A
360X
b 0.3 A B C 0.15 C
Notes:
1. Dimensioning and tolerance per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array
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Substrate Capacitors for the PC7447, 360 CBGA
Figure 26 shows the connectivity of the substrate capacitor pads for the PC7447, 360 CBGA. All capacitors are 100 nF. Figure 26. Substrate Bypass Capacitors for the PC7447, 360 CBGA
Pad Number A1 CORNER Capacitor C1 C2 C1-1 1 C1-2 C24-1 C24-2 C2-2 C3-2 C4-2 C5-2 C6-2 C7-2 C7-1 C22-1 C23-1 C22-2 C23-2 C8-2 C8-1 C9-2 C9-1 C12-2 C11-2 C10-2 C19-1 C20-1 C21-1 C19-2 C20-2 C21-2 C12-1 C11-1 C10-1 C18-2 C17-2 C16-2 C15-2 C14-2 C13-2 C18-1 C17-1 C16-1 C15-1 C14-1 C13-1 C2-1 C3-1 C4-1 C5-1 C6-1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 -1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND -2 VDD VDD OVDD VDD VDD VDD VDD VDD OVDD VDD VDD VDD VDD VDD VDD OVDD VDD OVDD VDD VDD OVDD VDD VDD VDD
Package Parameters for the PC7457, 483 CBGA
The package parameters are as provided in the following list. The package type is 29 x 29 mm, 483-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 29 mm x 29 mm 483 (22 x 22 ball array - 1) 1.27 mm (50 mil) - 3.22 mm 0.89 mm (35 mil)
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Figure 27 shows the pinout of the PC7457, 483 CBGA package as viewed from the top surface. Figure 28 shows the side profile of the CBGA package to indicate the direction of the top surface view. Figure 27. Pinout of the PC7457, 483 CBGA Package as Viewed from the Top Surface
1 A B C D E F G H J K L M N P R T U V W Y AA AB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 28. Side View of the CBGA Package
Substrate Assembly Encapsulant View Die
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.
Table 17. Pinout Listing for the PC7457, 483 CBGA Package
Signal Name A[0:35](2) AACK AP[0:4] ARTRY(3) AVDD BG BMODE0
(4)
Pin Number E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4, P1, P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4, AA1, D10, J4, G10, D9 U1 L5, L6, J1, H2, G5 T2 B2 R3 C6 C4 K1
Active High Low High Low - Low Low Low Low High Low Low Low High
I/O I/O Input I/O I/O Input Input Input Input Output Input Output Input Output Output
I/F Select(1) BVSEL BVSEL BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL
BMODE1(5) BR BVSEL CI
(3) (6)(7)
G6 R1 F3 K6 N1 AB15, T14, R14, AB13, V14, U14, AB14, W16, AA11, Y11, U12, W13, Y14, U13, T12, W12, AB12, R12, AA13, AB11, Y12, V11, T11, R11, W10, T10, W11, V10, R10, U10, AA10, U9, V7, T8, AB4, Y6, AB7, AA6, Y8, AA7, W8, AB10, AA16, AB16, AB17, Y18, AB18, Y16, AA18, W14, R13, W15, AA14, V16, W6, AA12, V6, AB9, AB6, R7, R9, AA9, AB8, W9 V1 AA2, AB3, AB2, AA8, R8, W5, U8, AB5 T6
CKSTP_IN CKSTP_OUT CLK_OUT
D[0:63]
High
I/O
BVSEL
DBG DP[0:7] DRDY(8) DTI[0:3])
(9) (10)
Low High Low High High Low
Input I/O Output Input Input I/O
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
P2, T5, U3, P6 B9 M4 A22, B1, B5, B12, B14, B16, B18, B20, C3, C9, C21, D7, D13, D15, D17, D19, E2, E5, E21, F10, F12, F14, F16, F19, G4, G7, G17, G21, H13, H15, H19, H5, J3, J10, J12, J14, J17, J21, K5, K9, K11, K13, K15, K19, L10, L12, L14, L17, L21, M3, M6, M9, M11, M13, M19, N10, N12, N14, N17, N21, P3, P9, P11, P13, P15, P19, R17, R21, T13, T15, T19, T4, T7, T9, U17, U21, V2, V5, V8, V12, V15, V19, W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5, AA17, AB1, AB22 B13, B15, B17, B19, B21, D12, D14, D16, D18, D21, E19, F13, F15, F17, F21, G19, H12, H14, H17, H21, J19, K17, K21, L19, M17, M21, N19, P17, P21, R15, R19, T17, T21, U19, V17, V21, W19, Y21 K2 A3
EXT_QUAL GBL
GND
-
-
N/A
GVDD(11) HIT(8) HRESET
- Low Low
- Output Input
N/A BVSEL BVSEL
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Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)
Signal Name INT L1_TSTCLK L2_TSTCLK L3VSEL(6)(7) L3ADDR[18:0] L3_CLK[0:1] L3_CNTL[0:1]
(10) (12)
Pin Number J6 H4 J2 A4 H11, F20, J16, E22, H18, G20, F22, G22, H20, K16, J18, H22, J20, J22, K18, K20, L16, K22, L18 V22, C17 L20, L22 AA19, AB20, U16, W18, AA20, AB21, AA21, T16, W20, U18, Y22, R16, V20, W22, T18, U20, N18, N20, N16, N22, M16, M18, M20, M22, R18, T20, U22, T22, R20, P18, R22, M15, G18, D22, E20, H16, C22, F18, D20, B22, G16, A21, G15, E17, A20, C19, C18, A19, A18, G14, E15, C16, A17, A16, C15, G13, C14, A14, E13, C13, G12, A13, E12, C12 AB19, AA22, P22, P16, C20, E16, A15, A12 V18, E18 P20, E14 F6 B8 A8, A11, B6, B11, C11, D11, D3, D5, E11, E7, F2, F11, G2, H9 B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7, J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11, U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19, AA4, AA15 A2, F7, C2, D4, H8 E6 B4 K7 Y1 L4, L8 G8 G1 D6 N8 L3 B7 J7 E4 H1 T1
Active Low High High High High High Low
I/O Input Input Input Input Output Output Output
I/F Select(1) BVSEL BVSEL BVSEL N/A L3VSEL L3VSEL L3VSEL
L3DATA[0:63]
High
I/O
L3VSEL
L3DP[0:7] L3_ECHO_CLK[0,2] L3_ECHO_CLK[1,3] LSSD_MODE MCP No Connect(14) OVDD PLL_CFG[0:4] PMON_IN(15) PMON_OUT QACK QREQ SHD[0:1] SMI SRESET SYSCLK TA TBEN TBST TCK TDI(7) TDO TEA
(7)(13)
High High High Low Low - - High Low Low Low Low Low Low Low - Low High Low High High High Low
I/O Input I/O Input Input - - Input Input Output Input Output I/O Input Input Input Input Input Output Input Input Output Input
L3VSEL L3VSEL L3VSEL BVSEL BVSEL N/A N/A BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
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Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)
Signal Name TEST[0:5](13) TEST[6] TMS
(7) (10)
Pin Number B10, H6, H10, D8, F9, F8 A9 K4 C1 P5 L1,H3,D1 F1, F4, K8, A5, E1 L2 J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15, M10, M12, M14, N9, N11, N13, N15, P10, P12, P14 G11, J8
Active - - High Low Low High High Low - -
I/O Input Input Input Input I/O Output I/O Output - -
I/F Select(1) BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL N/A N/A
TRST(7)(16) TS(3) TSIZ[0:2] TT[0:4] WT(3) VDD VDD_SENSE[0:1](17) Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD). For actual recommended value of VIN or supply voltages, see Table 3 on page 12. 2. Unused address pins must be pulled down to GND. 3. These pins require weak pull-up resistors (for example, 4.7 k) to maintain the control signals in the negated state after they have been actively negated and released by the PC7457 and other bus masters. 4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going high. 5. This signal must be negated during reset, by pull up to OVDD or negation by HRESET (inverse of HRESET), to ensure proper operation. 6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, pull-down resistors should be less than 250. 7. Internal pull up on die. 8. Ignored in 60x bus mode. 9. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode. 10. These input signals for factory use only and must be pulled down to GND for normal machine operation. 11. Power must be supplied to GVDD, even when the L3 interface is disabled or unused. 12. It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect performance. 13. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation. 14. These signals are for factory use only and must be left unconnected for normal machine operation. 15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software. 16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation. 17. These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage level present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
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Mechanical Dimensions for the PC7457, 483 CBGA
Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 CBGA package. Figure 29. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457, 483 CBGA Package
2X 0.2 D D1 D2 1 B 0.15 A Capacitor Region
A
D3 A1 CORNER
E3 E E4
E2 E1
2X 0.2 C 1 2 3 4 5 6 7 8 9 10111213141516 1718 1920 2122 AB AA Y W V U T R P N M L K J H G F E D C B A DIM D4 A A1 A2 A3 b D D1 A3 D2 D3 D4 A2 A1 A 0.35 A e E E1 E2 E3 E4
Millimeters MIN 2.72 0.80 1.10 - 0.82 29 BSC - 8.5 - 10.9 1.27 BSC 29 BSC - 8.5 - 9.55 12.5 - 8.4 9.75 12.5 - 8.4 11.1 MAX 3.20 1 1.30 0.6 0.93
483X
b 0.3 A B C 0.15 C
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side. A1 corner is designated with a ball missing from the array
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Substrate Capacitors for the PC7457, 483 CBGA
Figure 26 shows the connectivity of the substrate capacitor pads for the PC7457, 483 CBGA. All capacitors are 100 nF. Figure 30. Substrate Bypass Capacitors for the PC7457, 483 CBGA
A1 CORNER Pad Number Capacitor C1 C1-1 1 C1-2 C24-1 C24-2 C2-2 C3-2 C4-2 C5-2 C6-2 C7-2 C7-1 C22-1 C23-1 C22-2 C23-2 C8-2 C8-1 C9-2 C9-1 C12-2 C11-2 C10-2 C19-1 C20-1 C21-1 C19-2 C20-2 C21-2 C12-1 C11-1 C10-1 C18-2 C17-2 C16-2 C15-2 C14-2 C13-2 C18-1 C17-1 C16-1 C15-1 C14-1 C13-1 C2-1 C3-1 C4-1 C5-1 C6-1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 -1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND -2 OVDD VDD GVDD VDD VDD GVDD VDD VDD GVDD VDD VDD GVDD VDD VDD VDD OVDD VDD OVDD VDD VDD OVDD VDD VDD VDD
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System Design Information
PLL Configuration
This section provides system and thermal design recommendations for successful application of the PC7457. The PC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PC7457 is shown in Table 18 for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that don't comply with the 1 GHz column in Table 8 on page 20.
Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) Bus (SYSCLK) Frequency PLL_CFG[0:4] 01000 10000 10100 10110 10010 11010 01010 00100 00010 11000 01100 01111 01110 10101 10001 Bus-to-Core Multiplier 2x 3x 4x 5x 5.5x 6x 6.5x 7x 7.5x 8x 8.5x 9x 9.5x 10x 10.5x Core-to-VCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 600 (1200) 633 (1266) 667 (1333) 700 (1400) 600 (1200) 638 (1276) 675 (1350) 712 (1524) 750 (1500) 938 (1876) 623 (1245) 664 (1328) 706 (1412) 747 (1494) 789 (1578) 830 (1660) 872 (1744) 600 (1200) 650 (1300) 700 (1400) 750 (1500) 800 (1600) 850 (1700) 900 (1800) 950 (1900) 1000 (2000) 1050 (2100) 667 (1333) 733 (1466) 800 (1600) 866 (1730) 931 (1862) 1000 (2000) 1064 (2128) 1131 (2261) 1197 (2394) 1264 (2528) 667 (1333) 835 (1670) 919 (1837) 1002 (2004) 1086 (2171) 1169 (2338) 1253 (2505) 33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz
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Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (Continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) Bus (SYSCLK) Frequency PLL_CFG[0:4] 10011 00000 10111 11111 01011 11100 11001 00011 11011 00001 00101 00111 01001 01101 11101 00110 11110 Notes: Bus-to-Core Multiplier 11x 11.5x 12x 12.5x 13x 13.5x 14x 15x 16x 17x 18x 20x 21x 24x 28x PLL bypass PLL off Core-to-VCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 600 (1200) 667 (1334) 700 (1400) 800 (1600) 933 (1866) PLL off, SYSCLK clocks core circuitry directly PLL off, no core clocking occurs 600 (1200) 600 (1200) 650 (1300) 675 (1350) 700 (1400) 750 (1500) 800 (1600) 850 (1900) 900 (1800) 1000 (2000) 1050 (2100) 1200 (2400) 33.3 MHz 50 MHz 66.6 MHz 733 (1466) 766 (532) 800 (1600) 833 (1666) 865 (1730) 900 (1800) 933 (1866) 1000 (2000) 1066 (2132) 1132 (2264) 1200 (2400) 75 MHz 825 (1650) 863 (1726) 900 (1800) 938 (1876) 975 (1950) 1013 (2026) 1050 (2100) 1125 (2250) 1200 (2400) 83 MHz 913 (1826) 955 (1910) 996 (1992) 1038 (2076) 1079 (2158) 1121 (2242) 1162 (2324) 1245 (2490) 100 MHz 1100 (2200) 1150 (2300) 1200 (2400) 1250 (2500) 133 MHz 167 MHz
1. PLL_CFG[0:4] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7455; See "Clock AC Specifications" on page 20. for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9 on page 22). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
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4. In PLL-off mode, no clocking occurs inside the PC7455 regardless of the SYSCLK input.
The PC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock frequency of the PC7457. The core-to-L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the PC7457 core, and timing analysis of the circuit board routing. Table 19 shows various example L3 clock frequencies that can be obtained for a given set of core frequencies. Table 19. Sample Core-to-L3 Frequencies(1)
Core Frequency (MHz) 500 533 550 600 650 666 700 733 800 866 933 1000 1050(2) 1100(2) 1150 1200
(2) (2)
/2 250 266 275 300 325 333 350 367 400 433 467 500 525 550 575 600 638 650
/2.5 200 213 220 240 260 266 280 293 320 347 373 400 420 440 460 480 500 520
/3 167 178 183 200 217 222 233 244 266 289 311 333 350 367 383 400 417 433
/3.5 143 152 157 171 186 190 200 209 230 248 266 285 300 314 329 343 357 371
/4 125 133 138 150 163 167 175 183 200 217 233 250 263 275 288 300 313 325
/4.5 111 118 122 133 144 148 156 163 178 192 207 222 233 244 256 267 278 289
/5 100 107 110 120 130 133 140 147 160 173 187 200 191 200 209 218 227 236
/5.5 91 97 100 109 118 121 127 133 145 157 170 182 191 200 209 218 227 236
/6 83 89 92 100 108 111 117 122 133 145 156 166 175 183 192 200 208 217
/6.5 77 82 85 92 100 102 108 113 123 133 144 154 162 169 177 185 192 200
/7 71 76 79 86 93 95 100 105 114 124 133 143 150 157 164 171 179 186
/7.5 67 71 73 80 87 89 93 98 107 115 124 133 140 147 153 160 167 173
/8 63 67 69 75 81 83 88 92 100 108 117 125 131 138 144 150 156 163
1250(2) 1300(2) Notes:
1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the PC7457; see "L3 Clock AC Specifications" on page 24 for valid L3_CLK frequencies and for more information regarding the maximum L3 frequency. 2. These core frequencies are not supported by all speed grades; see Table 8 on page 20.
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PLL Power Supply Filtering
The AVDD power signal is provided on the PC7457 to provide power to the clock generation PLL. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 29 using surface mount capacitors with minimum effective series inductance (ESL) is recommended. The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias. The PLL power supply filter provided in the PC7457 RISC Microprocessor Hardware Specifications has been found to be less effective for Rev 1.1 devices with the low core voltages described in this specification. As a result, the recommended value for the resistor in the circuit is being evaluated and a new recommendation is indicated in Figure 31. Motorola continues to evaluate the filtering requirements of the PC7457 and will make updated recommendations as needed. Note that this recommendation applies to Rev. 1.1 devices only. Figure 31. PLL Power Supply Filter Circuit
400 VDD 2.2 F GND 2.2 F Low ESL surface mount capacitor AVDD
Decoupling Recommendations
Due to the PC7457 dynamic power management feature, large address and data buses, and high operating frequencies, the PC7457 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC7457 system, and the PC7457 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pin of the PC7457. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors: 100 - 330 F (AVX TPS tantalum or Sanyo OSCON).
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Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OV DD . Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the PC7457. If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and L3VSEL should be connected to BVSEL; the remainder of the L3 interface may be left unterminated. The PC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 30 on page 50). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 32. Driver Impedance Measurement
OVDD
Output Buffer DC Impedance
RN
SW2 Pad Data SW1
RP
OGND
Table 20 summarizes the signal impedance results. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 20. Impedance Characteristics with VDD = 1.5V, OVDD = 1.8V 5%, Tj = 5 - 85C
Impedance Typical Z0 Maximum Processor bus 33 - 42 31 - 51 L3 Bus 34 - 42 32 - 44 Unit
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Pull-up/Pull-down Resistor Requirements
The PC7457 requires high-resistive (weak: 4.7 k) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7457 or other bus masters. These pins are TS, ARTRY, SHDO, and SHD1. Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device operation. For the PC7447, 360 BGA, the pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are L1_TSTCLK and TEST[4]. For the PC7457, 483 BGA, the pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:5]; the pins that must be pulled down are L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 - 1 k) to prevent erroneous assertions of this signal. In addition, the PC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 - 1 k) if it is used by the system. This pin is CKSTP_OUT. If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250 (see Table 16 on page 40). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the PC7457 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7457 or by other receivers in the system. It is recommended that these signals be pulled up through weak (4.7 k) pull-up resistors by the system, or that they may be otherwise driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs are A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL. If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak pull-down resistors. If the PC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, don't require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are D[0:63] and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins don't require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The L3 interface does not normally require pull-up resistors.
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JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 31 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0 isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While Motorola recommends that the COP header be designed into the system as shown in Figure 31 on page 54, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. The COP header shown in Figure 31 adds many benefits - breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface - and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 31; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-tobottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 31 is common to all known emulators. The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a system and is an input to the PC7457 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7457 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.
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Figure 33. JTAG Interface Connection
From Target Board Sources (if any)
SRESET SRESET HRESET QACK 13 11 HRESET SRESET 10 k 10 k 10 k 10 k 0(5) OVDD OVDD OVDD OVDD HRESET
1 3 5 7 9 11
2 4 6 8 10 12
KEY
TRST 4 6 5(1) 15 Key 14(2) CHKSTP_IN 8 COP Header TMS 9 1 3 7 2 10 12(6) 16 QACK NC 2 k(3) 10 k(4) TDO TDI TCK CHKSTP_OUT 10 k 10 k VDD_SENSE 2 k 10 k
TRST OVDD OVDD CHKSTP_OUT OVDD OVDD CHKSTP_IN TMS TDO TDI TCK QACK OVDD
13 No Pin 15 16
COP Connector Physical Pin Out
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7457. Connect pin 5 of the COP header to OVDD with a 10 k pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK. 4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK. 5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of the part through a 0 isolation resistor. 6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an additional GND pin for improved signal integrity.
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Definitions
Datasheet Status Description
Table 21. Datasheet Status
Datasheet Status Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation results. This datasheet also contains characterization results. This datasheet contains final product specification. Validity Before design phase
Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values
Valid during the design phase
Valid before characterization phase
Valid before the industrialization phase Valid for production purposes
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification.
Life Support Applications
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.
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Ordering Information
PC (X) 7457 Prefix Prototype Type Application modifier(1) L: 1.3V 50 mV N: 1.1V 50 mV Max internal processor speed(1) 933 MHz 1000 MHz 1200 MHz (TBC) V G U 1000 L x Revision Level(1) Rev. B, C
Temperature Range: Tj(1) V: -40C, 110C M: -55C +125C
Package G: CBGA
Screening Level(1) U: Upscreening
PC (X) 7447 Prefix Prototype Type
V
G
U
1000
L
x Revision Level(1) Rev. B, C Application modifier(1) L: 1.3V 50 mV N: 1.1V 50 mV Max internal processor speed(1) 933 MHz 1000 MHz 1200 MHz (TBC)
Temperature Range: Tj(1) V: -40C, 110C M: -55C +125C
Package G: CBGA GH: HITCE (TBC)
Screening Level(1) U: Upscreening
Note:
1. For availability of the different versions, contact your local Atmel sales office.
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Document Revision History
Revision Number
Table 22 provides a revision history for this hardware specification.
Table 22. Document Revision History
Substantive Change(s) Figure 9 on page 22: Corrected pin lists for input and output AC timing to correctly show HIT as an output-only signal Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices. B Changed recommendations regarding use of L3 clock jitter in AC timing analysis in Section "L3 Clock AC Specifications" on page 24; the L3 jitter is now fully comprehended in the AC timing specs and does not need to be included in the timing analysis
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Table of Contents
Features ................................................................................................1 Description ...........................................................................................1 Screening ............................................................................................. 2 Block Diagram ......................................................................................3 General Parameters .............................................................................4 Features ................................................................................................4 Signal Description .............................................................................10 Detailed Specification .......................................................................11 Scope ..................................................................................................11 Applicable Documents ......................................................................11 Requirements .....................................................................................11
General ................................................................................................................ 11 Design and Construction .................................................................................... 11 Absolute Maximum Ratings ................................................................................ 11 Recommended Operating Conditions................................................................. 12 Thermal Characteristics ...................................................................................... 13
Electrical Characteristics ..................................................................19
Static Characteristics .......................................................................................... 19 Dynamic Characteristics ..................................................................................... 20
Preparation for Delivery ....................................................................37 Handling ..............................................................................................37 Package Mechanical Data .................................................................38
Package Parameters for the PC7447, 360 CBGA .............................................. 38
Pin Assignment ..................................................................................39 Pinout Listings................................................................................... 40 Mechanical Dimensions for the PC7447, 360 CBGA ......................43 Substrate Capacitors for the PC7447, 360 CBGA ...........................44
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Package Parameters for the PC7457, 483 CBGA ............................44 Mechanical Dimensions for the PC7457, 483 CBGA .......................49 Substrate Capacitors for the PC7457, 483 CBGA........................... 50 System Design Information .............................................................. 51 PLL Configuration .............................................................................51
PLL Power Supply Filtering ................................................................................ 54 Decoupling Recommendations ........................................................................... 54 Connection Recommendations........................................................................... 55 Output Buffer DC Impedance ............................................................................. 55 Pull-up/Pull-down Resistor Requirements .......................................................... 56 JTAG Configuration Signals ............................................................................... 57
Definitions .......................................................................................... 59 Datasheet Status Description ...........................................................59 Life Support Applications ................................................................. 59 Ordering Information......................................................................... 60 Document Revision History ..............................................................61
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